Synopsys Identify vN-2018.03 SP1 FOR WIN/LINUX Identify RTL Debugger Simulator-like Visibility into FPGA Hardware Operation The Identify® RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli. The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design. Key Features Ability to instrument and debug an advanced FPGA design directly from RTL source code Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit Visibility into the internal design while operating at full speed Display of debug results superimposed on top of RTL source, RTL structural view or with a waveform viewer Traverse debug sample buffer just like a simulator environment Instrument an FPGA-based ASIC prototype prior to device partitioning and planning via Synopsys Certify Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA Support for Altera, Microsemi and Xilinx devices Connects to live FPGA hardware using popular JTAG programming interfaces Automate instrumentation and debugging tasks with Tcl command interface Client-server communication option allows network access to PC attached to FPGA systems